Epic defines a new style of architecture that enables higher levels of instruction level parallelism ( ilp ) without unacceptable hardware complexity epic是一種顯性并行指令計(jì)算體系結(jié)構(gòu),主要思想是利用編譯器和處理器的協(xié)同能力來提高指令級(jí)并行度。
State-of-the-art microprocessors exploit instruction level parallelism ( ilp ) to achieve high performance on applications by searching for independent instructions in a dynamic window of instructions and executing them on a wide-issue pipeline 對(duì)于當(dāng)前軟件中占主要部分的串行程序而言,微處理器主要依靠開發(fā)程序的指令級(jí)并行(ilp)來提高性能。
Multithreaded microprocessor, which has many hardware contexts sharing an execution core, can efficiently exploit both the instruction level parallelism and thread level parallelism to acquire higher performance and better performance / power ratio 多份硬件現(xiàn)場共享一組執(zhí)行單元的多線程處理器能靈活地利用程序中的指令級(jí)并行和線程級(jí)并行,從而提供更好的性能。
One of the key elements to achieving higher performance in microprocessors is executing more instructions per cycle . however, dependencies among instructions, varying latencies of certain instructions, and execution resources constraints, limit this parallelism considerably . in order to exploit instruction level parallelism, processor should employ data dependence analysis to identify independent instructions that can execute in parallel 當(dāng)前,在微處理器體系結(jié)構(gòu)研究中,為了充分提高微處理器的處理性能,主要采用了指令級(jí)并行技術(shù)(ilp),指令級(jí)并行性的開發(fā)程度對(duì)發(fā)揮微處理器的硬件特性,提高程序運(yùn)行性能至為關(guān)鍵。